This invention relates to a complementary boundary-scan cell, and more particularly to a complementary boundary-scan cell in which there exist boundary-scan paths of a plurality of systems within the same chip.
As a conventional boundary-scan cell, there is a boundary-scan cell, e.g., disclosed in FIG. 1--1 of IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, p. 1-4. This boundary-scan cell comprises, as shown in FIG. 10, two multiplexers 1 and 2, and a scan register 3 including two D-type flip-flops 4 and 5.
In the normal operation mode, the Mode signal of logic "0" level is inputted to the control-terminal G1 of the multiplexer 2, and signals inputted from the input-port Signal-in are passed through the multiplexer 2 and are outputted to the exterior through the output-port Signal-out.
When this boundary-scan cell is in the test mode, the Mode signal is caused to be at logic "1" level.
When the boundary-scan cell is in the load mode, the Shift/load signal of logic "0" level is inputted to multiplexer 1, and a signal inputted from input-port Signal-in is inputted to data terminal of D-type flip-flop 4 of scan register 3 through multiplexer 1. When Clock A is inputted to clock terminal of D-type flip-flop 4, the signal inputted to the D-type flip-flop 4 is outputted and is transferred from the output-port Scan-out to the boundary-scan cell of the succeeding stage. In this way, the signals inputted from the exterior are sequentially transferred so that it reaches a plurality of boundary-scan cells arranged over the entirety of the system.
When the boundary-scan cell is in the shift mode, the Shift/load signal of logic "1" level (shift mode level) is inputted to multiplexer 1. A signal from input-port Scan-in is inputted to D-type flip-flop 4 of scan register 3 through multiplexer 1, and is outputted to the boundary-scan cell of the succeeding stage through output-port Scan-out at the timing when Clock A is given.
When signals are sequentially transferred to the boundary scan cell of the succeeding stage in this way, there results the state where the same signal is held on the output node of D-type flip-flop 4 of each scan register. In the scan register 3 of each boundary-scan cell, the signal held on the output node of D-type flip-flop 4 is outputted to the multiplexer 2 through D-type flip-flop 5 at the timing when Clock B is delivered to the D-type flip-flop 5. At this time, multiplexer 2 is supplied with the Mode signal of logic "1" level. Thus, a signal is outputted to the output-port Signal-out.
However, in the conventional boundary-scan cell, when there is at least one stuck fault such that, e.g., any signal line is short-circuited with power supply voltage VDD or ground voltage VSS, even if the internal logic circuit to be tested is normal and therefore operates non-defectively in the normal operation mode, it might be disadvantageously judged as defective at the time of testing the boundary-scan cell.